1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device, and more particularly to a manufacturing method of a semiconductor device including a transistor and a resistance element formed on an element isolation insulating film.
2. Description of the Background Art
LSI is constituted by transistors, resistance elements, and others. As one of the resistance elements, a resistance element formed by doping impurities into a polysilicon film (referred to as “polysilicon resistor” in this specification) is widely used. In general, the resistance value of the polysilicon resistor depends on the amount of impurities contained in the polysilicon film.
Hereinafter, a conventional manufacturing method of a semiconductor device including an n-channel MOSFET and a polysilicon resistor will be explained. This conventional manufacturing method of a semiconductor device includes the steps of (a) forming an element isolation insulating film inside an upper surface of a p-type silicon substrate, (b) forming a gate insulating film of MOSFET on the upper surface of the silicon substrate within an element forming region, (c) forming a first polysilicon film containing no doped impurities on the entire surface, (d) by patterning the first polysilicon film, forming a second polysilicon film functioning as a polysilcon resistor on the element isolation insulating film and forming a third polysilicon film functioning as a gate electrode of MOSFET on the gate insulating film, (e) forming an LDD region (which may be referred to as “extension region”) of MOSFET by ion-implanting n-type first impurities from a direction substantially normal to the upper surface of the silicon substrate (i.e., from the vertical direction), (f) forming a pocket region of MOSFET by ion-implanting p-type second impurities from a direction inclined relative to the above-described vertical direction, (g) forming a sidewall spacer on a side surface of the second polysilicon film, (h) by ion-implanting n-type third impurities from the direction substantially normal to the upper surface of the silicon substrate, forming a source-drain region of MOSFET, and setting a resistance value of the polysilicon resistor by ion-implanting the third impurities into the second polysilicon film, and (i) performing a thermal treatment to activate the first to third impurities implanted in the silicon substrate.
The techniques relating to the manufacturing method of a polysilicon resistor are, for example, disclosed in Japanese Patent No. 3153921, Japanese Patent Application Laid-open No. 59-16361(1984), Japanese Patent Application Laid-open No. 6-314770 (1994), and Japanese Patent Application Laid-open No. 11-251520(1999).
Recently, from the needs of realizing high-performance semiconductor devices, IC chips mounting both a digital circuit and an analog circuit are widely used. Especially, from the reason that the resistance element is utilized for a bias setting or the like of a transistor, the analog circuit is required to accurately set its resistance value.
However, according to the conventional manufacturing method of a semiconductor device, not only the third impurities but also the first and second impurities are ion-implanted into the second polysilicon film. Namely, a plurality kinds of impurities are implanted in the second polysilicon film. Furthermore, part of the first to third impurities contained in the second polysilicon film diffuses out of the second polysilicon film (i.e., causes external diffusion) when they are subjected to the thermal treatment in the step (i). Furthermore, there is the possibility that a significant temperature difference is caused within a wafer surface during the thermal treatment. In this case, the external diffusion amount of the impurities will disperse on the wafer surface.
As described above, according to the conventional manufacturing method of a semiconductor device, it was difficult to set the resistance value of a polysilicon resistor to a desired value. Furthermore, the resistance value disperses in the wafer surface even if resistance elements are the same in size.